1. Field of the Invention
The present invention relates to the field of integrated circuit fabrication. Particularly in lithographic processes for improving line edge roughness (LER) and reduced critical dimensions (CD) for lines and trenches.
2. Discussion of Related Art
The semiconductor industry is continually pursuing smaller and smaller geometries of the structures used in semiconductor devices. As the device geometries become smaller, more devices are fabricated into the same area of semiconductor substrate. Therefore, the number of interconnect lines in the same area of substrate must also increase, thus requiring that the sizes of the interconnect lines and the spacing between the interconnect lines also decrease in size. This results in the need to reduce both the geometries, i.e. the critical dimensions (CD), of the interconnect lines and the pitch between interconnect lines. Furthermore, as lithographic processes are pushed to the limit, interconnect lines suffer from line edge roughness (LER). Interconnect lines having a high LER may result in degraded performance of the device, possibly due to larger line resistances, increased intra-line capacitances and cross-talk, and may even result in short and/or open circuits.
Accordingly, there exists a need for an improved lithographic process that can reduce CDs, provide tighter pitches between interconnect lines, and reduce LER.